What Should You Do to Get the Most Out of Your Time and Resources (Simulations)



If you haven't checked out Greg Wilson's presentation, spend 15 minutes on that. It's well worth it.

Philosophy

  • Think global, act local
  • Do your top-level sim from day 1. This is the agile methodology. Use simplified views for cells to ”act local” (This top-level approach concept was from a Chinese design manager from NXP-Freescale. Same guy who used to advise making every cell's dimensions multiples of the digital standard-cell, to enable super compact layouts)
  • Block-level sim should have only one Design Under Test (DUT). Don’t ”verify” hookup in a ”block-level sim”. That should always use the actual hookup — i.e., full-chip, with unneeded cells bound-to-open in the Hierarchy Editor (yes, deactivation (SHlFT—DEL) is found to be necessary because of Cadence limitations —slowdown with a large design)
  • Keep thinking flexible. It’s okay to admit a past workflow was inferior and embrace new methodology. It takes moral courage

Spectre

  • Use spectre as much as possible (i.e., avoid APS, Spectre-X, AMS)-- minimize license cost
  • When node count blows up large array, too much digital, then think about going to APS or AMS with Verilog
  • When you are in design/debug mode, always save all nodes, always apply compression to wildcard saves (Choose Analyses > Transient > Options > Output) (explicit saves are always saved without compression for accuracy), turn OFF final OP point, etc; may be okay to use APS to reduce sim time from 2 min to 1 min for productivity.
  • When submitting large jobs, monte-carlo, etc, reduce overhead to a minimum only save select nodes, reduce #cores to min, etc run overnight; Simulation > Options > Analog > Check does not have "both" or "file " for destination (disk usage); think about license cost (avoid APS)
  • Set rise/fall times for your sources (clks - wait! Why are you putting out a clock from an analogLib source???!! If you're in spectre only, to conserve licenses, good:)). Ditto for veriloga logic gate models. Make the simulator's job as easy as posible!

AMS

  • Use Verilog as much as possible! (means: force cellviews to verilog AMAP) This runs the fastest and, when hookup is right, reduces analog-node-count (load on spectre) to minimum. Use couple of sims with transistor-level and Veriloga to identify interface issues, and then move to Verilog to check connectivity
  • Aim for a total run time of 2-3 minutes and go through as many iterations identifying design issues as you can in a day.
  • Use the profilers to generate helpful messages in the xrun.log about which nodes are causing slowdown
  • Try to move those to digital, or, if not, ensure the veriloga is optimized (see veriloga slide) ‘
  • Always keep clocks in digital. The minute the net touches an analog block, you’re in trouble. So, also run the I/O buffers in Verilog (not veriloga!). Remember, high frequency clocks should NEVER touch analog
  • No need to set accuracy to anything other than "liberal” for top-level!
  • If you make a change to the config on a large design (never saw an issue on small designs) then use the ”delete the tmp dir button” (icon : eraser on the far right along with the X for delete and the file-save icon) (have to descend into the test in Assembler). It's a clue if your register write doesn't work. Why? Go figure :)

Data - Profiling

  • Simulation > Options > Analog (Spectre): Check "detailed" for "diagnose" ("Check" tab)
  • Simulation > Options > AMS Simulator: Check "Generate runtime profile" ("Miscellaneous" tab)
  • Simulation > Options > Analog(Spectre) : Check "detailed" for "print statistics report" ("Annotation" tab)
  • You never know when you'll see something useful, that gets you that order of magnitude boost in resource conservation (run time, disk usage, etc)

Hooks (get more for less)

  • How to get the TB to take an action when something deep down in the DUT happens? (Eg. only start I2C write activity after the POR has been released)
  • Ans : analogLib/deepprobe to bring a buried node to TB level
  • Read the Cadence app note on support.cadence.com (signing up is something you should do on Day 1!!) to get this right if the node is digital (Simulation>Options>AMS Simulator>Netlister tab > check "netlist.vams with OOMR" for "Generate iprobe.in". Also, if the node is analog and applied to a digital block at TB level, you might get surprised (deepprobe fails). I found that interposing an ahdlLib/and_gate solves this issue

veriloga/Verilog-AMS

  • Never feed a continuous signal into a transition filter (Cadence has a good presentation on veriloga and pitfalls). This can slow down your sim
  • Logic gates in ahdlLib have ancient veriloga - use as is with caution - you can do better. No issue for small sims/TBs. 
  • Problem is that the @cross or @above statements don’t specify TTOL and VTOL which default to values that can result in a lot of timesteps near the transitions. Valuetol might default to RELTOL
  • Better to copy over (if not already copied over) and bring out TTOL,VTOL as params
  • Do you care if actual event is 100 ps different from when AMS says it is? If it happened at V_thresh +/— 5 mV? No? Then relax the settings in your code and help the simulator out :)
  • Verilog-AMS : only assign to reg inside @<event> driven block


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