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Showing posts from March, 2026

You Want to Name Wires After Your Instance. How?

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The video shows an example of an incorrect application (since only one instance name is used - you have to apply the shortcut on a per-instance basis) and then the right one. Click on the image to see it in its original size. Why use this? It's a time-saver for the case of having two DUTs in your test-bench for the sake of comparison. Also, sometimes you have two blocks in your design that are identical, but still need unique controls - for register-bits, etc. You can select some of the labels - no need to select all of them. Find this one and more at  https://github.com/ananthchellappa/SKILL

What Should You Do to Get the Most Out of Your Time and Resources (Simulations)

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If you haven't checked out Greg Wilson's presentation , spend 15 minutes on that. It's well worth it. Philosophy Think global, act local Do your top-level sim from day 1. This is the agile methodology. Use simplified views for cells to ”act local” (This top-level approach concept was from a Chinese design manager from NXP-Freescale. Same guy who used to advise making every cell's dimensions multiples of the digital standard-cell, to enable super compact layouts) Block-level sim should have only one Design Under Test (DUT). Don’t ”verify” hookup in a ”block-level sim”. That should always use the actual hookup — i.e., full-chip, with unneeded cells bound-to-open in the Hierarchy Editor (yes, deactivation (SHlFT—DEL) is found to be necessary because of Cadence limitations —slowdown with a large design) Keep thinking flexible. It’s okay to admit a past workflow was inferior and embrace new methodology. It takes moral courage Spectre Use spectre as much as possible (i.e., av...