veriloga Debugging - $strobe Vs $display

$strobe vs $display in Verilog and Verilog-A: Understanding the Difference

Summary: $display prints immediately when called, while $strobe prints at the end of the current simulation time step. In mixed-signal simulations, $strobe often produces cleaner, chronologically ordered logs.

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Why timing of print statements matters

In both Verilog and Verilog-A, simulation events can occur at the same time. This is common in mixed-signal designs where analog events, digital edges, and timers may coincide. Printing in the middle of these updates (as $display does) can lead to logs that look out of order. $strobe avoids this by printing only after all events for that time step have completed.

Rule of thumb: Use $display for immediate, step-by-step debugging; use $strobe for clean, time-aligned logs.

Key differences

Task	When it prints	Best for	Drawbacks
$display	Immediately when executed	Inspecting execution order inside a time step	Logs may be out of order when events share the same time
$strobe	At the end of the current simulation time	Consistent, ordered logs in mixed-signal simulations	Doesn’t show intra-step sequencing

Example: Digital Verilog

// Multiple events at the same time
module demo;
  initial begin
    #10 $display("display at t=%0t (A)", $time);
    #0  $display("display at t=%0t (B, same time)", $time);
    #0  $strobe ("strobe  at t=%0t (end-of-time)", $time);
  end
endmodule

Run this and you’ll see both $display lines first, then the $strobe line, even though they all happen at the same simulation time.

Example: Verilog-A / Verilog-AMS (Phase-Frequency Detector snippet)

analog begin
  @(cross(V(ref)-vth, +1)) begin
    up_state = 1;
    if (dn_state && !reset_pending) begin
      reset_pending = 1;
      t_fire = $abstime + t_reset;
      $display("armed reset at %g s", t_fire);
    end
  end

  @(timer(t_fire)) begin
    if (reset_pending) begin
      up_state = 0; dn_state = 0; reset_pending = 0;
      $strobe("PFD delayed reset at %g s", $abstime);
    end
  end
end

Guidelines

• Prefer $strobe for final event logs, especially when many events share the same simulation time.
• Use $display for in-depth debugging of event ordering.
• In mixed-signal models, $strobe prevents misleading print order caused by analog/digital scheduling.

Common pitfalls

• Nesting timers: In some simulators, @(timer(...)) inside another event may never trigger. Use a time variable and handle the timer at the top level.
• Short pulses: Set a small enough maxstep to resolve short events in your logs.
• Edge detection: Make sure your signal actually crosses the threshold in @(cross(...)).

Bottom line: In Verilog, Verilog-A, and Verilog-AMS, $display shows you what’s happening right now; $strobe shows you the state after everything for that time is done.