When You Want to Get Cycle-to-Cycle Jitter at PLL Output Due to the Reference Oscillator
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Designers Guide : Phase Noise and Jitter prediction, by Ken Kundert |
Converting Phase Noise to Cycle-to-Cycle Jitter in a PLL
When designing or analyzing phase-locked loops (PLLs), one key metric of interest is the RMS cycle-to-cycle jitter at the output. Given phase noise data (typically in dBc/Hz) for the reference oscillator, how do we estimate the jitter after the PLL processes it?
🎯 Goal
Estimate RMS cycle-to-cycle jitter (in seconds or picoseconds) at the output of a PLL, based on:
- Measured or simulated phase noise data (dBc/Hz vs. offset frequency)
- PLL dynamics: natural frequency (
fn
), damping ratio (ζ
), divider ratio (N
) - Carrier frequency (
fc
)
🧠Step-by-Step Breakdown
1. Read Phase Noise Data
Extract two columns from a CSV file:
f_offset
: Offset frequencies (e.g., 1 kHz, 10 kHz)L_dbc
: Phase noise values in dBc/Hz
2. Convert dBc/Hz to Linear Phase Noise PSD
Use:
S_phi_in = 2 * 10 ** (L_dbc / 10)This converts logarithmic SSB noise into linear power spectral density (rad²/Hz). The factor 2 accounts for the total noise power from both sidebands.
3. Apply the PLL Transfer Function
The PLL acts as a low-pass filter for reference phase noise. The closed-loop transfer function from reference to output (in the s-domain) is:
H(s) = N / (1 + 2ζ·s/ωₙ + s²/ωₙ²)
where:
N
is the divider ratioζ
is the damping factorωₙ = 2Ï€·fn
is the natural frequency in rad/s
In the frequency domain, we compute the squared magnitude:
|H(j2Ï€f)|² = ωₙ⁴ / [ (ωₙ² - ω²)² + (2ζωₙω)² ]
This determines how phase noise at each offset frequency is shaped by the PLL. Importantly:
- Low-frequency noise (inside loop bandwidth) is passed to the output.
- High-frequency noise (outside bandwidth) is suppressed.
4. Convert Phase PSD to Time PSD
To obtain timing jitter, convert phase PSD to time PSD using:
S_tau = S_phi_out / (2Ï€·fc)²This gives the jitter power spectral density in units of seconds squared per Hz (s²/Hz).
5. Apply Cycle-to-Cycle Jitter Filter
Cycle-to-cycle jitter captures variations from one clock period to the next. The filtering effect is modeled by:
H_ccj(f)² = 4·sin²(Ï€fT)where
T = 1 / fc
is the clock period. This emphasizes jitter components near the Nyquist frequency and suppresses slow variations.
6. Integrate Over Frequency
Finally, integrate the filtered PSD to obtain total jitter power:
rms_ccj = sqrt( ∫ S_ccj(f) df )The square root converts from variance to RMS jitter.
✅ Final Output
The script computes and prints the RMS cycle-to-cycle jitter in picoseconds:
RMS Cycle-to-Cycle Jitter: X.XXX ps
🧠Summary
Stage | Description |
---|---|
dBc/Hz → rad²/Hz | Convert log-scale phase noise to linear PSD |
Apply PLL filter | Pass low-frequency reference noise, suppress high-frequency |
Convert to time PSD | Translate phase noise to equivalent timing noise |
Cycle-to-cycle filter | Extract only variations from one clock period to the next |
Integrate | Sum jitter energy across frequency |
Sqrt | Convert jitter power to RMS jitter |
This methodology connects frequency-domain measurements (phase noise) to time-domain performance (jitter), enabling precise prediction of clock behavior in high-speed systems.
Here is a script that you can use as (fn is the 3dB bandwidth of the PLL in Hz)
$ python3 pll_jitter.py phase_noise_saved.csv --N 256 --zeta 0.9 --fn 2e3 --fc 32768
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