HIdden States in Your Behavioral Model

Rewrite the module to remove the hidden state or if you confirm this hidden state will not affect the simulation result, you can ignore those hidden states in RF analysis by adding attribute 'ignore_hidden_state' before the module declaration. For example, 

(* ignore_hidden_state *)

module moduleA

Yes, that's the exact syntax you need to use - that line works so much magic. It's strange that Cadence would offer behavioral models to customers in its ahdlLib library that aren't "ready to roll" in terms of NOT having hidden states.



https://designers-guide.org/analysis/PLLnoise+jitter.pdf

https://community.cadence.com/cadence_technology_forums/f/rf-design/26712/how-to-avoid-hidden-state-in-veriloga-model-for-spectrerf

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