A Bindkey to Focus (Raise above other windows) the CIW

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Plotting Device Parameters (gm, vdsat, etc) Vs Time or Temp

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I feel like this has gotten more complicated. I think it might have been easier 10 years ago. Then again, I could be w. Go to resource: How to save and plot operating point parameters for Spectre simulator from ADE Explorer/Assembler In Explorer, you go to Outputs > To be Saved > Select OP Parameters Now, the schematic window is active and you can click on instances and each gets highlighted as you do. These get populated in the Assembler Outputs Setup You will see that the "Type" is not signal but oppoint. If you click on the Details field, it splits into two - the /whatever/deviceName is on the left, and on the new field on the right, you can enter parameters appropriate for that device, like vdsat, vth, cgs, etc.  The UI is very poor, but, on the right of this field is a button you can actually click to choose from a list. It'll even run a sim if necessary! If you want these plotted, you have to check the box to the right under the Plot column. Other gems Finding...
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veriloga Debugging - $strobe Vs $display

$strobe vs $display in Verilog and Verilog-A: Understanding the Difference Summary: $display prints immediately when called, while $strobe prints at the end of the current simulation time step. In mixed-signal simulations, $strobe often produces cleaner, chronologically ordered logs. Why timing of print statements matters In both Verilog and Verilog-A, simulation events can occur at the same time. This is common in mixed-signal designs where analog events, digital edges, and timers may coincide. Printing in the middle of these updates (as $display does) can lead to logs that look out of order. $strobe avoids this by printing only after all events for that time step have completed. Rule of thumb: Use $display for immediate, step-by-step debugging; use $strobe for clean, time-aligned logs. Key differences Task When it prints Best for Drawbacks $display Immediately when executed Inspecting execution ...
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When You Want to Get Cycle-to-Cycle Jitter at PLL Output Due to the Reference Oscillator

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Caution - the script does not provide the correct result. You expect cycle-to-cycle to be a high-frequency phenomenon - and therefore, to not depend on the oscillator phase-noise or jitter. But the script will show a large value for c2c jitter on the PLL output. If you can figure it out, please post/comment. Designers Guide : Phase Noise and Jitter prediction , by Ken Kundert Converting Phase Noise to Cycle-to-Cycle Jitter in a PLL When designing or analyzing phase-locked loops (PLLs), one key metric of interest is the RMS cycle-to-cycle jitter at the output. Given phase noise data (typically in dBc/Hz) for the reference oscillator, how do we estimate the jitter after the PLL processes it? 🎯 Goal Estimate RMS cycle-to-cycle jitter (in seconds or picoseconds) at the output of a PLL , based on: Measured or simulated phase noise data (dBc/Hz vs. offset frequency) PLL dynamics: natural frequency ( fn ), damping ratio ( ζ ), divider ratio ( N ) Carrier frequency ( fc ) ...
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