Cadence Tips and Tricks

Srinath - IIT-K's finest Cadence Library Manager > Design Manager > SOS Design Manager In the Cells pane on the left, find your cell and select On the right, select the view(s) you want to search for. Then, change the "Show" field on the top to "cellviews that use me" And then click the Display button.

Rewrite the module to remove the hidden state or if you confirm this hidden state will not affect the simulation result, you can ignore those hidden states in RF analysis by adding attribute 'ignore_hidden_state' before the module declaration. For example,  (* ignore_hidden_state *) module moduleA Yes, that's the exact syntax you need to use - that line works so much magic. It's strange that Cadence would offer behavioral models to customers in its ahdlLib library that aren't "ready to roll" in terms of NOT having hidden states. https://designers-guide.org/analysis/PLLnoise+jitter.pdf https://community.cadence.com/cadence_technology_forums/f/rf-design/26712/how-to-avoid-hidden-state-in-veriloga-model-for-spectrerf

What if you have too many "sim err" cells that you need to hide? What can you enter in the filter field to accomplish this? Ans: Hit the sort button - it might show you all the "sim err" cells and nothing else (if you have too many). Hit it again so you sort in the other order and now you'll see what is the max or min. So, just use that in the filter field with a > or <. Put another way, if you are going to Detail Transpose so you can debug a particular min or max (which you saw in your Yield view), then you already have an idea of the number. So, when you're filtering all you have to do is > min - epsilon or < max + epsilon QED

Problem - you are interested in the output expressions that you set up, but, unfortunately, ADE-L (Assembler debug env) displays them interspersed with waveforms (signals) that *have* to be saved.. You want to see all your output expressions on the top of the Outputs pane. Thank you chatGPT:  https://github.com/ananthchellappa/python/blob/master/cadence/fix_ADE_out_ord.py

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